Give a two dimentional array of registors that contains intensity value. It is feed to you one registor per cycle. How to design a hardware using FPGA to calculate the average of the 9 registors including 8 that locate right beside the center one.
Using overloaded operators and a node class with expression and literal subtypes. You overload operators for the expression class as well as the literal class where you either return the literal or further expand the expression