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Cpu Design Engineer Interview Questions
85 cpu design engineer interview questions shared by candidates
Design a bitstream pattern detection finite state machine in the HDL of your choice.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
Design a Reorder Buffer on the Register Transfer Level.
Where do you see yourself in 5 years?
Explain ASIC Design Flow? Explain about Placement congestion and how to reduce it? Write a TCL script for searching a slack value which is violated in a report and write those values in another file?
Describe how to build a flip-flop
Questions were FSM , types Draw 10X11 sequence detector using mealy and more machine Verilog code for FSM Fifo FIFO depth calculation
Lots of questions on OoO processor and Caches Learn more than what is given in your coursework
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