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Hardware Design Engineer Interview Questions


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1. question obout low power design, start from easy question and after it was answerd the more complex details were added. 2. build FSM divider by 5, start from simple solution and after that more complex constraints and limitations were added

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My answers were fluent, at some stage of the second question it was a little bit complex limitation but i solved it.

What does this circuit do? (Composed of a switch, diode, inductor and resistor) Where does the current go when the switch is opened?

How would you design a low pass filter, and what does the frequency response look like?

First interview was an HR interview on phone. The interview lasted 30-40 mins. This interview is mainly a screening interview to know about personality, work ethics, technical background and work/travel abroad eligibilities. If your interview went well, you can expect to hear back from HR to schedule a next round of interview in 1-2 days. Second interview was onsite, with 3 Senior Engineers(1-1.5 hour each). They asked me lot of question about my technical background, past projects and some problem questions from Digital design and FPGA. The general trend in the problem statements was - initially a problem is given, if you solve it more conditions are added, and so on. The ones I remember are following:

There were some general questions related to my projects and my experiences. Some technical questions that I can remember are: 1) Given a diagram of some basic arithmetic operations and asked to simplify it. Basically, you try to reduce the area by utilizing one less multiplier. A follow up question was given the latency for each operation and ask how to improve the latency. The answer is basically to pipeline the combinational circuit by using flip flops to split into to stages. 2) A basic timing question regarding the max frequency the flip-flop can operate at given the various D-Q, C-Q, hold and t-combination timings. Then a follow up question asks if one of the time is changed, how would it affect the circuit. Basically the answer is to reduce the frequency to allow correct operation. Another follow up was if the hold time is not satisfied, would changing the clock frequency help. The answer to that question is no and to get that answer you need to draw the timing diagram and see that changing the frequency does not help. 3) Another question involving multiple flip-flops and asked to draw timing diagram of various points in the circuit. 4) A buffer over-flow problem and how to solve it. Basically, you had to figure out that the input side of buffer is writing at a higher rate than the reading side of the buffer. Basically, you had to delay the sending function for a period of time after sending certain amount of packets of data.

1. What do you know about Sierra Wireless's business ? 2. Tell us what was your contribution in *insert project name* and what did you learn from it ? 3. What are your strengths and weaknesses ? 4. What is a low noise filter and how does it work ?

What are techniques to extend the bandwidth of a CML differential pair.

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Describe the schematic and explain how it work

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Questions about high-speed PCB design, TDR analysis, different serial data buses (I2C, SMB and LAN).

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