Verification engineer interview questions shared by candidates
explain setup and hold time with figure and some example and then interviewer added some circuitry and asked to solver setup and hold violation in circut
Setup and hold violations are caused when datapath (logic) is too slow or too fast, respectively, compared to clock cycle. In the first case need to make driving FF stronger and decrease wire delays, in the second case the opposite.
Pipelining is also another way to resolve setup time violations.