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Verification Engineer Interview Questions


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explain setup and hold time with figure and some example and then interviewer added some circuitry and asked to solver setup and hold violation in circut

2 Answers

Setup and hold violations are caused when datapath (logic) is too slow or too fast, respectively, compared to clock cycle. In the first case need to make driving FF stronger and decrease wire delays, in the second case the opposite.

Pipelining is also another way to resolve setup time violations.

About your current job. PBX, IP telephone, SIP

1 Answer

How many golf balls fit inside a school bus?

1 Answer

Write a decimal to hex function in C

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how can you decide a clock cycle by 3, use verilog to impalement it

1 Answer

random testing using c

1 Answer

Mostly hardware related. Such as design basic hardware components using Verilog. Also debugging C++ language programs.

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they focused a lot on OOP, which is unexpected given the title that I applied.

1 Answer

What did you do at your previous co-op employer?

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