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      PLL Design Engineer, ASIC IP Development Interview

      May 6, 2025
      Anonymous interview candidate
      New York, NY
      No offer
      Neutral experience
      Difficult interview

      Application

      I applied through an employee referral. The process took 2 weeks. I interviewed at Apple (New York, NY) in Mar 2025

      Interview

      45 min technical interview with hiring manager. asked about my previous work, based on a digital PLL. PLL for RFIC design, focused on fractional-n pll knowledge after the first round, 6 hours interview is the final process but I didn't get an offer

      Interview questions [4]

      Question 1

      Pros and cons of vernier TDC
      Answer question

      Question 2

      Compare the analog and digital PLL, pros and cons
      Answer question

      Question 3

      loop stability calculation, dominant pole
      Answer question

      Question 4

      DCO circuit diagram. analog approach and digital approach
      Answer question