bit req, ack, clk; sequence s_req req; endsequence sequence s_ack ack; endsequence property ack_after_req; @(posedge clk) s_req |-> ##[1:2] s_ack; //change the [1:2] accordingly endproperty assert property (ack_after_req) $display("ack is within [1:2] after reset");