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      ASIC Design Verification Engineer Interview

      Jul 15, 2025
      Anonymous interview candidate
      Bengaluru
      No offer
      Positive experience
      Easy interview

      Application

      I applied through an employee referral. The process took 2 weeks. I interviewed at Meta (Bengaluru) in Jul 2025

      Interview

      1 screening round of 45 minutes if thorugh then ,3 technical rounds of 45 mins each and atlast 1 HR round of 45 mins. Screening for basic knowledge and coding. Three technical where in depth knowledge and coding will be tested.

      Interview questions [1]

      Question 1

      Constraint randomization based question linking to AXI and memory filling
      Answer question

      Other ASIC Design Verification Engineer interview reviews for Meta

      ASIC Design Verification Engineer Interview

      Aug 25, 2025
      Anonymous interview candidate
      Bengaluru
      No offer
      Positive experience
      Easy interview

      Application

      I interviewed at Meta (Bengaluru)

      Interview

      One basic round the 5-6 loop interviews.if we qualify 1 round loops interviews will be there.all questions are basis.mostly about sv constraints. Last round will be focused on test plan creation.

      Interview questions [1]

      Question 1

      Read after write sequence implementation
      Answer question

      ASIC Design Verification Engineer Interview

      Feb 7, 2025
      Anonymous interview candidate
      Bengaluru
      No offer
      Neutral experience
      Average interview

      Application

      I applied online. The process took 5 days. I interviewed at Meta (Bengaluru) in Feb 2025

      Interview

      45 mins technical online interview. Interviewer was in PST timezone. Interview on coderpad. The interviewer asked about my professional journey so far and got started with coding interview. An initial document was shared with me prior to setting up the interview that listed the topics they can possibly ask in the interview for preparation. They asked me to fill up 4-5 timeslots where I can take an interview and in about 1-2 days the interview slot was finalized.

      Interview questions [3]

      Question 1

      Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
      Answer question

      Question 2

      Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
      Answer question

      Question 3

      Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
      1 Answer
      2

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