Preliminary round consists of a written paper testing your skill in VLSI, Comp arch, Digi and general aptitude. The next round is the interview where again your basics are tested and then there is a talk with the HR representative.
Interview questions [1]
Question 1
The questions are based on the performance in your paper
I applied through other source. The process took 1 day. I interviewed at Arm (Austin, TX) in Dec 2014
Interview
I had four technical interviews with four different members of my future team one after the other followed by a "get-to-know you" interview by my future boss. Each of the technical interviews differed based on the knowledge and skills of the interviewer. i.e. one asked questions about programming in C++ another asked about computer architecture and microarchitecture, etc.
I applied through university. I interviewed at Arm (Austin, TX) in Sep 2014
Interview
It's a ARM draft day. On that day, there were about 20 candidates. In the morning, they introduced a lot about the company, the product, the benefit. Then everyone had 4 interviews from noon to afternoon. The interviews are not very easy, more than what I learn in the course. But interviewer are nice and will give you the hint to answer the question.
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Social Recruiting Manager
I applied online. The process took 3 weeks. I interviewed at Arm (Austin, TX) in Mar 2014
Interview
I'd applied online for the position and got a call after 2 months. There was a two hour phone screen by two senior design engineers which consisted of basic digital VLSI questions like logical effort, impact of scaling, types of power, crosstalk issues and some basic questions on number system conversions. A week later, I was invited for an onsite interview at Austin which consisted of 7 rounds of 1:1 interview including an HR round. I felt the interviews covered almost all the aspects of ASIC design flow ranging from RTL coding to layout. Overall, the questions were mostly basic stuffs from timing(setup/hold), verilog coding, IR drop issues, clock tree synthesis, placement, routing etc.
Interview questions [1]
Question 1
Some questions on clock tree where you have to come up with a possible design solution in order to keep the clock latency low.