I applied online. The process took 3 weeks. I interviewed at NVIDIA (San Jose, CA) in Sep 2015
Interview
Two phone interviews followed by on-site interview. The first phone interview is about PLL design an d the second has more general circuit questions. On the on-site interview, there were mostly general analog circuit questions and no PLL/SerDes questions. The interview is not very difficult. I wait three weeks for the decision. The people in the group are nice and the working environment is good.
Phone screening interview with HR first then the online technical interview with hiring manager for resume screen. It toook about 30 min. I got an email of interview result after 2 weeks.
Interview questions [1]
Question 1
He requested to compare with LPDDR and HBM and how to control impedance control.
I applied online. The process took 4 days. I interviewed at NVIDIA
Interview
I was interviewed by phone twice. In the first interview, I was interviewed by an experienced mixed-signal designer. His questions follows a certain flow, like device physics about depletion region, common source amplifiers, current mirror, noise analysis, gain-boosting amplifiers, 2.5bit-per stage in pipelined ADC, sigma-delta modulator, and noise profile of free running VCO and PLL transfer functions. Some of the topics were chosen from my resume. The second interview was held by a senior design engineer. She sent me a pdf to solve circuit problems, mainly focused on large signal analysis, output impedance analysis, feedback analysis and miller compensation. I did not do well in this part so I got kicked off.
Interview questions [1]
Question 1
What is MDAC gain in 2.5bit-per-stage in pipelined ADC? I understood the answer after the interview... In the continuous-time sigma-delta modulator, can the gain-boosting amplifier be designed with a lower bandwidth? This is really hard to understand for new college grads if you don't have experience in designing that... Why is the intrinsic gain of BJT is higher than that of MOSFET? You need to review that the p-substrate in NMOS is lightly doped and and therefore more sensitive to reverse bias, and this is also where channel length modulation comes into the picture. Some of the circuit problems are really novel and I have to come up with new techniques to analyze it.
