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      Design Verification Engineer Interview

      Sep 9, 2022
      Anonymous interview candidate
      Bengaluru
      No offer
      Positive experience
      Difficult interview

      Application

      I applied through an employee referral. The process took 6 days. I interviewed at HCLTech (Bengaluru) in Sep 2022

      Interview

      Definitely went on well and was a great interview. The interviewer was polite and made me feel comfortable. The interview was about 1 hour to 1 hour 15 minutes. Overall experience was good.

      Interview questions [1]

      Question 1

      About Electronic basics and Communcation basics
      Answer question

      Other Design Verification Engineer interview reviews for HCLTech

      Design Verification Engineer Interview

      Jun 3, 2025
      Anonymous interview candidate
      Bengaluru
      No offer
      Positive experience
      Average interview

      Application

      I applied through a staffing agency. The process took 1 day. I interviewed at HCLTech (Bengaluru) in Jun 2025

      Interview

      There was a written test and followed by two round of interviews for candidates who passed the written test. They focused more on Verilog code and asked questions about the projects.

      Interview questions [1]

      Question 1

      Verilog code for basic circuits
      Answer question

      Design Verification Engineer Interview

      Aug 15, 2022
      Anonymous employee
      Hyderābād
      Accepted offer
      Positive experience
      Average interview

      Application

      I applied through a recruiter. I interviewed at HCLTech (Hyderābād) in Jul 2021

      Interview

      I have gone through 2 rounds. 1. Technical interview Here mostly I got questions from my projects , sv and uvm related questions 2. Managerial round ( same as technical interview). The manager mostly asked the questions like , how we actually do the verification. Steps to do for verification process. Process of debugging. He gave me one question and ask me how will I debug that.

      Interview questions [1]

      Question 1

      Uvm phases and explain them
      Answer question