As 8086 does 2-stage pipelining, its architecture is divided into two units: 1. Bus Interface Unit (BIU) 2. Execution Unit (EU) BUS INTERFACE UNIT (BIU) 1. It provides the interface of 8086 to other devices. 2. It operates w.r.t. Bus cycles . This means it performs various machine cycles such as Mem Read, IO Write etc to transfer data with Memory and I/O devices. 3. It performs the following functions: a) It generates the 20-bit physical address for memory access. b) Fetches Instruction from memory. c) Transfers data to and from the memory and IO. d) Supports Pipelining using the 6-byte instruction queue. The main components of the BIU are as follows: a) SEGMENT REGISTERS: 1) CS Register CS holds the base (Segment) address for the Code Segment. All programs are stored in the Code Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Code Segment. Eg: If CS = 4321H then CS × 10H = 43210H è Starting address of Code Segment. CS register cannot be modified by executing any instruction except branch instructions 2) DS Register DS holds the base (Segment) address for the Data Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Data Segment. Eg: If DS = 4321H then DS × 10H = 43210H è Starting address of Data Segment. 3) SS Register SS holds the base (Segment) address for the Stack Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Stack Segment. Eg: If SS = 4321H then SS × 10H = 43210H è Starting address of Stack Segment. 4) ES Register ES holds the base (Segment) address for the Extra Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Extra Segment. Eg: If ES = 4321H then ES × 10H = 43210H è Starting address of Extra Segment. b) Instruction Pointer (IP register) It is a 16-bit register. It holds offset of the next instruction in the Code Segment 6-Byte Pre-Fetch Queue {Pipelining – 4m} It is a 6-byte FIFO RAM used to implement Pipelining. Fetching the next instruction while executing the current instruction is called Pipelining. BIU fetches the next “six instruction-bytes” from the Code Segment and stores it into the queue. Execution Unit (EU) removes instructions from the queue and executes them. The queue is refilled when atleast two bytes are empty as 8086 has a 16-bit data bus. Pipelining increases the efficiency of the µP. Pipelining fails when a branch occurs, as the pre-fetched instructions are no longer useful. Hence as soon as 8086 detects a branch operation, it clears/discards the entire queue. Now, the next six bytes from the new location (branch address) are fetched and stored in the queue and Pipelining continues.