Skip to contentSkip to footer
  • Community
  • Jobs
  • Companies
  • Salaries
  • For employers
      Notifications

      Loading...

      Elevate your career

      Discover your earning potential, land dream jobs, and share work-life insights anonymously.

      employer cover photo
      employer logo
      employer logo

      Apple

      Engaged employer

      About
      Reviews
      Pay and benefits
      Jobs
      Interviews
      Interviews
      Related searches: Apple reviews | Apple jobs | Apple salaries | Apple benefits | Apple conversations
      Apple interviewsApple Design Verification Engineer interviewsApple interview


      Glassdoor

      • About / Press
      • Awards
      • Blog
      • Research
      • Contact Us
      • Guides

      Employers

      • Free Employer Account
      • Employer Centre
      • Employers Blog

      Information

      • Help
      • Guidelines
      • Terms of Use
      • Privacy and Ad Choices
      • Do Not Sell Or Share My Information
      • Cookie Consent Tool
      • Security

      Work With Us

      • Advertisers
      • Careers
      Download the App

      • Browse by:
      • Companies
      • Jobs
      • Locations
      • Communities
      • Recent posts

      Copyright © 2008-2026. Glassdoor LLC. "Glassdoor," "Worklife Pro," "Bowls" and logo are proprietary trademarks of Glassdoor LLC.

      Company Bowl sample

      Want the inside scoop on your own company?

      Check out your Company Bowl for anonymous work chats.

      Bowls

      Get actionable career advice tailored to you by joining more bowls.

      Followed companies

      Stay ahead in opportunities and insider tips by following your dream companies.

      Job searches

      Get personalised job recommendations and updates by starting your searches.

      Design Verification Engineer Interview

      Nov 19, 2015
      Anonymous interview candidate
      Palo Alto, CA
      No offer
      Neutral experience
      Difficult interview

      Application

      I applied online. The process took 3 weeks. I interviewed at Apple (Palo Alto, CA) in Nov 2015

      Interview

      The phone interview was quite easy, mainly focusing on my resume. For the onsite interview, I had 6 interviewers and 4 of them asked normal questions but 2 of them asked very difficult questions with very few hints... The result came out really fast just 10 min after I finished my interview

      Interview questions [1]

      Question 1

      1. In a certain protocol why the ready signal is inout instead of out? 2. About the refresh in DDR2 3. FSM 4. System Verilog, Verilog, C, Perl, (also questions about OOP) 5. Bit operation
      1 Answer
      1

      Other Design Verification Engineer interview reviews for Apple

      Design Verification Engineer Interview

      Mar 11, 2026
      Anonymous interview candidate
      San Diego, CA
      No offer
      Positive experience
      Difficult interview

      Application

      I interviewed at Apple (San Diego, CA)

      Interview

      There were 1 screening and 6 panel rounds and it was difficult especially UVM part also they AMBA protocols basic design questions like fsm fifo and all and more focus on constraints

      Interview questions [1]

      Question 1

      UVM based questions and Assertions and constraints
      Answer question

      Design Verification Engineer Interview

      Apr 24, 2026
      Anonymous interview candidate
      Sunnyvale, CA
      No offer
      Neutral experience
      Easy interview

      Application

      I applied online. I interviewed at Apple (Sunnyvale, CA) in Mar 2026

      Interview

      I had a screening round that started directly without any introduction. I was asked questions about my resume, mainly about my projects. After that, I was given a coding question.

      Design Verification Engineer Interview

      Feb 1, 2026
      Anonymous interview candidate
      San Jose, CA
      No offer
      Neutral experience
      Average interview

      Application

      I interviewed at Apple (San Jose, CA)

      Interview

      first asking about the tool experience, asking about UVM knowledge like how and when to connect the sequencer and driver and what is their handshake , how do you deal with CDC problems, how to do the STA analysis, then final having a coding question

      Interview questions [1]

      Question 1

      implementation of driver class based on the figure they gave
      Answer question